Most electronic systems include a number of networked elements (components) such as hardware and software that form the system. In most systems there is a layer responsible for communication between the different components that form a networked element as well as between the different networked elements themselves. This layer is typically referred to as the InterProcessor Communication (IPC) layer.
Several protocols have been introduced in the last few years to deal with interprocessor communications. One example of an IPC product is PCI AGP Controller (PAC) that integrates a Host-to-PCI bridge, Dynamic Random Access Memory (DRAM) controller and data path and an Accelerated Graphics Port (AGP) interface. Another example of an IPC product is the OMAP™ platforms. Neither of these platforms provides much if any support above the hardware level and provides little design flexibility at the lower level component or channel levels (physical layer).
The PAC platforms for example, are closed architectures and are embedded into the Operating System's TAPI layer, with the IPC code not being accessible to developers. Therefore, these platforms do not extend to the component levels they also do not allow for dynamic assignment of IPC resources, hardware support capabilities, or multi-node routing, etc. as well as not allowing for the dynamic assignment of the IPC resources. Given the above, a need thus exists in the art for an IPC protocol that can provide a solution to some of these shortcomings in the prior art.